Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

While Loop

A sequential statement. The statements inside the while loop are executed repeatedly while the condition is True.

Syntax

  [LoopLabel:] while Condition loop
    SequentialStatements...
  end loop [LoopLabel];
    

Where

See Sequential Statement

Rules

The Condition is tested at the start of the loop and once after each iteration, but not during the execution of the Statements.

Synthesis

Not generally synthesizable. Some tools do allow while loops containing wait statements to describe implicit finite state machines, but this is not recommended practice.

Example

  while Going loop
    Count := Count + 1;
    wait until Clock = '1';
  end loop;
    
(See Access, Process, TEXTIO)

See Also

For Loop, Loop, Exit, Next